In a prior art monitoring arrangement, a parallel-mode signal entering the arrangement is converted to a serial-mode signal, which is supplied to series-connected registers where the signal is monitored. In the monitoring, the signal can be searched for different bit patterns, for example.
A signal converted to serial mode consists of bit sequences of a predetermined length, i.e. bytes. The prior art arrangement does not allow a parallel-mode signal to be directly monitored if the frame phase of the signal converted from parallel to serial mode does not coincide with byte boundaries. Problems have occurred particularly in situations where the arrangement receives a signal from a parallel bus that has a different phase than the signal the bus is carrying to the arrangement. The problem has been alleviated by buffering of the signal coming to the arrangement. However, the signal must be buffered to a considerable extent, whereby other problems, such as delay, arise due to the buffering.
The prior art arrangement requires a clock signal proportional to the bit rate of the incoming signal, the clock signal being used for transferring the signal to the arrangement. If the average bit rate of the input signal is for example doubled, the frequency of the clock signal used for transferring the input signal must be doubled. Due to the forming of a clock signal proportional to the data rate of the input signal the arrangement is, however, considerably complex.